Austemper Design Systems
Analyzing, Enhancing and Verifying Robustness of Design
Austemper Design Systems is an electronic design automation tools company that provides a comprehensive tool-suite to Analyze, Augment and Verify the functional safety features in System-on-Chip and ASIC components.
Our mission is to provide the ASIC vendors with a one-stop solution for meeting their functional safety requirements.
Our industry leading tools provide our customers with a scalable solution to gain functional safety certification for products serving the Automotive, Industrial, Medical and Enterprise markets.
- Founded 2015 and based in Austin, Texas
- Experienced Team of veteran semiconductor professionals
- Engaged with most major IC suppliers and semiconductor IP vendors
- Working closely with Tier 1-backed Automotive IC supplier.
The Management Team:
Sanjay Pillay : Founder & CEO
Sanjay has 22 years of experience in Management and Engineering in Enterprise, Automotive, Consumer SoC development. He founded Austemper in march 2015, to address the need for a complete, automated, scalable safety engineering tool set, which he found to be lacking. In his various roles, Sanjay has championed and developed the advanced methodologies and flows to improve accuracy, productivity and predictability in ASIC development. Prior to founding Austemper, he headed the world wide Enterprise SSD controller SoC development at HGST/STEC, where he also set up the Austin design center. Sanjay has also served as a functional safety consultant. Sanjay lead the SoC architecture and world wide SoC development organizations at Trident/NXP/Conexant delivering the most power efficient STB SoC. He was the head of Audio ASIC development at Maxim. Sanjay was head of ASIC development for DSP and embedded products at Cirrus Logic delivering high volume products to tier-1 customers. Prior to that he has held engineering roles spanning the entire development flow at Cirrus Logic working on consumer and automotive products. His first engineering job was at Ross Technology, a startup developing high performance SPARC Processors. His drive for continuous improvement has resulted in inventions in circuit design, power management, signal processing and algorithms with 12 issued and multiple pending patents. He has a B.Tech in electrical engineering from the Indian Institute of Technology, New Delhi, India and a M.S in electrical engineering from Clemson University, Clemson, SC.
Arun Gogineni : Development Lead
Arun has 12 years of experience in Engineering in Automotive and Consumer SoC development at Entropic/Trident/ NXP/Conexant along with consulting roles at Altera and Ikanos. He has had the pleasure and pain of working on inherited designs and making design modifications for memory wrapper, DFT and security modules, along with the responsibility of gate-level simulation and emulation of boot sequences for the SoCs, which provided him with a unique perspective on the challenges of design updates for testability, scalability and speed for gate level simulations and portability to emulation platforms, driving his desire to create a complete, automated and scalable tool set to address the pain points. He has a B.Tech in electrical engineering from the Jawaharlal Nehru Technological University, Kakinada, India and a M.Tech from the National Institute of Technology Rourkela, India.
The main office of Austemper Design Systems is located at:
Phone: +1 (737) 226-0990