Motivation

Functional Safety is a key area of concern for mission-critical systems and is codified in IEC/ISO standards using both qualitative and quantitative metrics into defined Safety Integrity Levels (SIL).  Systems across the medical, industrial and automotive sectors confront the twin challenge of meeting stringent SIL specifications in an increasingly complex design space.

Safety Engineering for ASIC and silicon IP vendors looking to meet a particular Automotive SIL (ASIL) classification by demonstrating reliable, repeatable and verifiable functional safety mechanisms designed into the ASIC and silicon IP.

Existing solutions for the analysis of ASICs and IPs for functional safety compliance is heavily dependent on expert intervention. The estimation of diagnostic coverage is heuristic-driven and subject to considerable interpretation latitude which makes this process non-repeatable and time consuming.

The addition of functional safety mechanisms into the ASIC and IPs are largely hand driven implementations with ancillary support from scripts, which makes this inherently error prone impacting the resources and schedules.

To verify the functional safety coverage, a fault injection campaign is executed at the gate level which are cumbersome and the cycle-time for simulation limits the design-size and the exhaustiveness of the campaign. Today’s fault campaigns for a typical automotive ASIC, as an illustration, are limited to a micro-controller subsystem. Larger designs call for a innovative approach to address the limitations.

The Austemper tools were designed from the ground up to address these unique challenges of demonstrating reliable, repeatable and verifiable functional safety mechanisms in a SoC, ASIC and IPs to meet the desired Safety Integrity Levels (SIL).